.travis.yml

@@ -0,0 +1,21 @@
+language: ruby
+branches:
+    only:
+        - master
+script:
+    - git clone https://github.com/asciidoctor/asciidoctor.git
+    - cd asciidoctor
+    - bundle install
+    - cd ..
+    - pwd
+    - mkdir build
+    - asciidoctor/bin/asciidoctor main.asciidoc -o build/index.html
+    - asciidoctor/bin/asciidoctor draft-cahpv3.asciidoc -o build/draft-cahpv3.html
+    - asciidoctor/bin/asciidoctor draft-rv16kv2.asciidoc -o build/draft-rv16kv2.html
+    - asciidoctor/bin/asciidoctor draft-rv32kv1.asciidoc -o build/draft-rv32kv1.html
+deploy:
+    provider: pages:git
+    edge: true
+    local_dir: build/
+    token:
+      secure: "bkhKJHkgGqoleoSmsVK+ZTc+zf16P0sMlev1IFw4UzaU/PBXZgtXFIcZ1gntuyra+8jyzzeJal0HyYROVx7/TJbrmgmq4fDY469t+0r5onE5OEfklfLCIAdwUIfE3QZ9SQclYOzeVmN5Qdp/+H7I0hVqz7d2RwZcGid/RethywiVKxU+4/+sKYumn0330P1xZnuPTbtjIv5ohlWtVdWsTuj3jwKP7vOkSmIL1zxG5FLhFccEveSc7UYNqYH3OTnVQcJiHejG3VaBYzGD9td93lDEjvBMEfqLfxqX13U4F1pUfLoE6dreVmtjJ5mi+wzWMqFJlYtaG6efP74SAyGRjyxZ/gYYO5CIB/FX8yjd4urfiaKeWkC++HeNlrRG3Z+lFaCuc1Z6c6w1yudweG7Ah/bTsBTX2SxD2NNy7IiDMJxv0Yr5fKMvTFG6mO7swRAtc3kgdMyNd2kAQSYRSOVo2z61Pr64mrO6NhB0ySNOTaYWCU9aBiLkvXPeMhXnT2xa3e8kXYCNP0Khehy1BfMogEUWT3HGGxaiZCw7TG+tLkrZx6d9MkTm2J0KddMtku8GVW5aQ31Z0upKUJr0953fvfXnDPreyZgcY8V/mKIxfw0Ogf8LH7PSC/t43KcXgCaOfm55HYDm8HrQeHcE1ZIoHNxIwA5fVa0YtJdRVpAjLnQ="

Gemfile

@@ -0,0 +1,5 @@
+source "https://rubygems.org"
+
+gem "guard"
+gem "guard-shell"
+gem "asciidoctor"

Gemfile.lock

@@ -0,0 +1,48 @@
+GEM
+  remote: https://rubygems.org/
+  specs:
+    asciidoctor (2.0.10)
+    coderay (1.1.2)
+    ffi (1.12.2)
+    formatador (0.2.5)
+    guard (2.16.2)
+      formatador (>= 0.2.4)
+      listen (>= 2.7, < 4.0)
+      lumberjack (>= 1.0.12, < 2.0)
+      nenv (~> 0.1)
+      notiffany (~> 0.0)
+      pry (>= 0.9.12)
+      shellany (~> 0.0)
+      thor (>= 0.18.1)
+    guard-compat (1.2.1)
+    guard-shell (0.7.1)
+      guard (>= 2.0.0)
+      guard-compat (~> 1.0)
+    listen (3.2.1)
+      rb-fsevent (~> 0.10, >= 0.10.3)
+      rb-inotify (~> 0.9, >= 0.9.10)
+    lumberjack (1.2.4)
+    method_source (1.0.0)
+    nenv (0.3.0)
+    notiffany (0.1.3)
+      nenv (~> 0.1)
+      shellany (~> 0.0)
+    pry (0.13.0)
+      coderay (~> 1.1)
+      method_source (~> 1.0)
+    rb-fsevent (0.10.3)
+    rb-inotify (0.10.1)
+      ffi (~> 1.0)
+    shellany (0.0.1)
+    thor (1.0.1)
+
+PLATFORMS
+  ruby
+
+DEPENDENCIES
+  asciidoctor
+  guard
+  guard-shell
+
+BUNDLED WITH
+   1.17.2

Guardfile

@@ -0,0 +1,7 @@
+Bundler.require :default
+
+guard 'shell' do
+  watch(/^main\.asciidoc$/) {|m|
+    Asciidoctor.convert_file m[0], safe: :safe
+  }
+end

README.md

@@ -0,0 +1,35 @@
+# 手を動かせばできるLLVMバックエンド チュートリアル（WIP）
+
+<a rel="license" href="http://creativecommons.org/licenses/by/4.0/"><img alt="Creative Commons License" style="border-width:0" src="https://i.creativecommons.org/l/by/4.0/80x15.png" /></a>
+[![Build Status](https://travis-ci.org/ushitora-anqou/write-your-llvm-backend.svg?branch=master)](https://travis-ci.org/ushitora-anqou/write-your-llvm-backend)
+
+自作ISAのためのLLVMバックエンドをイテレーティブに作ります。鋭意執筆中。
+
+[ここからmasterが読めます。](https://ushitora-anqou.github.io/write-your-llvm-backend/)
+
+## 下書き
+
+この文章は、2019年度に艮 鮟鱇が作成したLLVMバックエンドの、自分用メモがベースになっています。
+このメモをブラッシュアップしてまともな文章として公開する予定でしたが、
+その作業が遅れているため、一旦メモのまま公開します。
+
+- [RV32Kv1](https://ushitora-anqou.github.io/write-your-llvm-backend/draft-rv32kv1.html)
+- [RV16Kv2](https://ushitora-anqou.github.io/write-your-llvm-backend/draft-rv16kv2.html)
+- [CAHPv3](https://ushitora-anqou.github.io/write-your-llvm-backend/draft-cahpv3.html)
+
+## ビルド方法
+
+Asciidoctorのmasterを持ってきて`asciidoctor main.asciidoc`とかする。
+
+文章を書くときに、ファイルを更新するたびにコンパイルしたい場合は
+付属の`Gemfile`と`Guardfile`を使って`bundle exec guard`とかする。
+要`bundle install`。Epiphany（GNU Web）を入れて生成されたHTMLを見ると、
+更新時にリロードしてくれるので便利。詳細は[公式ドキュメント](https://asciidoctor.org/docs/editing-asciidoc-with-live-preview/)を参照。
+
+## Author
+
+[艮 鮟鱇（うしとら あんこう／Ushitora Anqou）](https://anqou.net/)
+
+## LICENSE
+
+<a rel="license" href="http://creativecommons.org/licenses/by/4.0/"><img alt="Creative Commons License" style="border-width:0" src="https://i.creativecommons.org/l/by/4.0/88x31.png" /></a><br />This work is licensed under a <a rel="license" href="http://creativecommons.org/licenses/by/4.0/">Creative Commons Attribution 4.0 International License</a>.

ref.adoc

@@ -0,0 +1,174 @@
+[bibliography]
+== 参考文献
+
+- [[[github_riscv-llvm_docs_01,1]]] https://github.com/lowRISC/riscv-llvm/blob/master/docs/01-intro-and-building-llvm.mkd
+- [[[llvm_getting-started,2]]] https://llvm.org/docs/GettingStarted.html
+- [[[clang_gettings-started,3]]] https://clang.llvm.org/get_started.html
+- [[[asciidoctor_user-manual,4]]] https://asciidoctor.org/docs/user-manual/
+- [[[riscv,5]]] https://riscv.org/
+- [[[riscv_specifications,6]]] https://riscv.org/specifications/
+- [[[fox-llvm,7]]] 『きつねさんでもわかるLLVM〜コンパイラを自作するためのガイドブック〜』（柏木 餅子・風薬・矢上 栄一、株式会社インプレス、2013年）
+- [[[github_riscv-llvm_docs_02,8]]] https://github.com/lowRISC/riscv-llvm/blob/master/docs/02-starting-the-backend.mkd
+- [[[github_riscv-llvm_patch_02,9]]] https://github.com/lowRISC/riscv-llvm/blob/master/0002-RISCV-Recognise-riscv32-and-riscv64-in-triple-parsin.patch
+- [[[github_riscv-llvm,10]]] https://github.com/lowRISC/riscv-llvm
+- [[[youtube_llvm-backend-development-by-example,11]]] https://www.youtube.com/watch?v=AFaIP-dF-RA
+- [[[msyksphinz_try-riscv64-llvm-backend,12]]] http://msyksphinz.hatenablog.com/entry/2019/01/02/040000_1
+- [[[github_riscv-llvm_patch_03,13]]] https://github.com/lowRISC/riscv-llvm/blob/master/0003-RISCV-Add-RISC-V-ELF-defines.patch
+- [[[github_riscv-llvm_patch_04,14]]] https://github.com/lowRISC/riscv-llvm/blob/master/0004-RISCV-Add-stub-backend.patch
+- [[[github_riscv-llvm_patch_06,15]]] https://github.com/lowRISC/riscv-llvm/blob/master/0006-RISCV-Add-bare-bones-RISC-V-MCTargetDesc.patch
+- [[[github_riscv-llvm_patch_10,16]]] https://github.com/lowRISC/riscv-llvm/blob/master/0010-RISCV-Add-support-for-disassembly.patch
+- [[[llvm-writing_backend-operand_mapping,17]]] https://llvm.org/docs/WritingAnLLVMBackend.html#instruction-operand-mapping
+- [[[llvm-writing_backend,18]]] https://llvm.org/docs/WritingAnLLVMBackend.html
+- [[[github_riscv-llvm_patch_07,19]]] https://github.com/lowRISC/riscv-llvm/blob/master/0007-RISCV-Add-basic-RISCVAsmParser.patch
+- [[[github_riscv-llvm_patch_08,20]]] https://github.com/lowRISC/riscv-llvm/blob/master/0008-RISCV-Add-RISCVInstPrinter-and-basic-MC-assembler-te.patch
+- [[[llvm-tablegen,21]]] https://llvm.org/docs/TableGen/index.html
+- [[[github_riscv-llvm_patch_09,22]]] https://github.com/lowRISC/riscv-llvm/blob/master/0009-RISCV-Add-support-for-all-RV32I-instructions.patch
+- [[[llvm_dev_ml-tablegen_definition_question,23]]] http://lists.llvm.org/pipermail/llvm-dev/2015-December/093310.html
+- [[[llvm_doxygen-twine,24]]] https://llvm.org/doxygen/classllvm_1_1Twine.html
+- [[[llvm-tablegen-langref,25]]] https://llvm.org/docs/TableGen/LangRef.html
+- [[[github_riscv-llvm_docs_05,26]]] https://github.com/lowRISC/riscv-llvm/blob/master/docs/05-disassembly.mkd
+- [[[github_riscv-llvm_patch_11,27]]] https://github.com/lowRISC/riscv-llvm/blob/master/0011-RISCV-Add-common-fixups-and-relocations.patch
+- [[[github_riscv-llvm_docs_06,28]]] https://github.com/lowRISC/riscv-llvm/blob/master/docs/06-relocations-and-fixups.mkd
+- [[[github_riscv-llvm_patch_13,29]]] https://github.com/lowRISC/riscv-llvm/blob/master/0013-RISCV-Initial-codegen-support-for-ALU-operations.patch
+- [[[speakerdeck-llvm_backend_development,30]]] https://speakerdeck.com/asb/llvm-backend-development-by-example-risc-v
+- [[[llvm-code_generator,31]]] https://llvm.org/docs/CodeGenerator.html
+- [[[llvm-code_generator-target_independent_code_gen_alg,32]]] https://llvm.org/docs/CodeGenerator.html#target-independent-code-generation-algorithms
+- [[[llvm-code_generator-selectiondag_instruction_selection,33]]] https://llvm.org/docs/CodeGenerator.html#selectiondag-instruction-selection-process
+- [[[github_riscv-llvm_patch_15,34]]] https://github.com/lowRISC/riscv-llvm/blob/master/0015-RISCV-Codegen-support-for-memory-operations.patch
+- [[[cpu0,35]]] https://jonathan2251.github.io/lbd/
+- [[[elvm-llvm_backend,36]]] https://github.com/shinh/llvm/tree/elvm
+- [[[elvm-slide,37]]] http://shinh.skr.jp/slide/llel/000.html
+- [[[github_riscv-llvm_patch_16,38]]] https://github.com/lowRISC/riscv-llvm/blob/master/0016-RISCV-Codegen-support-for-memory-operations-on-globa.patch
+- [[[github_riscv-llvm_patch_17,39]]] https://github.com/lowRISC/riscv-llvm/blob/master/0017-RISCV-Codegen-for-conditional-branches.patch
+- [[[todai_llvm_backend,40]]] https://github.com/cpu-experiment-2018-2/llvm/tree/master/lib/Target/ELMO
+- [[[todai_llvm_backend-article,41]]] http://uenoku.hatenablog.com/entry/2018/12/25/044244
+- [[[github_riscv-llvm_patch_18,42]]] https://github.com/lowRISC/riscv-llvm/blob/master/0018-RISCV-Support-for-function-calls.patch
+- [[[llvm-langref,43]]] http://llvm.org/docs/LangRef.html
+- [[[fpga_develop_diary,44]]] http://msyksphinz.hatenablog.com/
+- [[[llvm-anton_korobeynikov_2012,45]]] https://llvm.org/devmtg/2012-04-12/Slides/Workshops/Anton_Korobeynikov.pdf
+- [[[llvm-welcome_to_the_back_end_2017,46]]] https://www.youtube.com/watch?v=objxlZg01D0
+- [[[ean10-howto-llvmas,47]]] https://www.embecosm.com/appnotes/ean10/ean10-howto-llvmas-1.0.html
+- [[[lowrisc-devmtg18,48]]] https://www.lowrisc.org/llvm/devmtg18/
+- [[[LLVMBackend_2015_03_26_v2,49]]] http://www.inf.ed.ac.uk/teaching/courses/ct/other/LLVMBackend-2015-03-26_v2.pdf
+- [[[rui-compilerbook,50]]] https://www.sigbus.info/compilerbook
+- [[[krister-writing_gcc_backend,51]]] https://kristerw.blogspot.com/2017/08/writing-gcc-backend_4.html
+- [[[llvm-ml-129089,52]]] http://lists.llvm.org/pipermail/llvm-dev/2019-January/129089.html
+- [[[llvm-langref-datalayout,53]]] https://llvm.org/docs/LangRef.html#langref-datalayout
+- [[[github-frasercrmck_llvm_leg,54]]] https://github.com/frasercrmck/llvm-leg/tree/master/lib/Target/LEG
+- [[[llvm_doxygen-InitMCRegisterInfo,55]]] https://llvm.org/doxygen/classllvm_1_1MCRegisterInfo.html#a989859615fcb74989b4f978c4d227a03
+- [[[llvm-programmers_manual,56]]] http://llvm.org/docs/ProgrammersManual.html
+- [[[llvm-writing_backend-calling_conventions,57]]] https://llvm.org/docs/WritingAnLLVMBackend.html#calling-conventions
+- [[[riscv-calling,58]]] https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf
+- [[[llvm_dev_ml-how_to_debug_instruction_selection,59]]] http://lists.llvm.org/pipermail/llvm-dev/2017-August/116501.html
+- [[[fpga_develop_diary-20190612040000,60]]] http://msyksphinz.hatenablog.com/entry/2019/06/12/040000
+- [[[llvm_dev_ml-br_cc_questions,61]]] http://lists.llvm.org/pipermail/llvm-dev/2014-August/075303.html
+- [[[llvm_dev_ml-multiple_result_instrs,62]]] https://groups.google.com/forum/#!topic/llvm-dev/8kPOj-_lbGk
+- [[[stackoverflow-frame_lowering,63]]] https://stackoverflow.com/questions/32872946/what-is-stack-frame-lowering-in-llvm
+- [[[llvm_dev_ml-selecting_frame_index,64]]] https://groups.google.com/d/msg/llvm-dev/QXwtqgau-jA/PwnHDF0gG_oJ
+- [[[fpga_develop_diary-llvm,65]]] https://github.com/msyksphinz/llvm/tree/myriscvx/impl90/lib/Target/MYRISCVX
+- [[[llvm-github_cd44ae,66]]] https://github.com/llvm/llvm-project/commit/cd44aee3da22f9a618f2e63c226bebf615fa8cf8
+- [[[llvm_phabricator-d43752,67]]] https://reviews.llvm.org/D43752
+- [[[llvm-compilerwriterinfo,68]]] https://llvm.org/docs/CompilerWriterInfo.html
+- [[[wikipedia-The_Gleaners,69]]] https://en.wikipedia.org/wiki/The_Gleaners
+- [[[github_riscv-llvm_patch_20,70]]] https://github.com/lowRISC/riscv-llvm/blob/master/0020-RISCV-Support-and-tests-for-a-variety-of-additional-.patch
+- [[[llvm_phabricator-d47422,71]]] https://reviews.llvm.org/D47422
+- [[[llvm-extendingllvm,72]]] https://llvm.org/docs/ExtendingLLVM.html
+- [[[llvm_dev_ml-001264,73]]] http://lists.llvm.org/pipermail/llvm-dev/2004-June/001264.html
+- [[[llvm_phabricator-d42958,74]]] https://reviews.llvm.org/D42958
+- [[[compiler_rt,75]]] https://compiler-rt.llvm.org/
+- [[[github-riscv_compiler_rt,76]]] https://github.com/andestech/riscv-compiler-rt
+- [[[github_riscv-llvm_patch_27,77]]] https://github.com/lowRISC/riscv-llvm/blob/master/0027-RISCV-Support-stack-frames-and-offsets-up-to-32-bits.patch
+- [[[llvm_phabricator-d44885,78]]] https://reviews.llvm.org/D44885
+- [[[llvm_phabricator-d45859,79]]] https://reviews.llvm.org/D45859
+- [[[llvm-langref-poison_value,80]]] http://llvm.org/docs/LangRef.html#poisonvalues
+- [[[github-emscripten-issues-34,81]]] https://github.com/emscripten-core/emscripten/issues/34
+- [[[switch_lowering_in_llvm,82]]] http://fileadmin.cs.lth.se/cs/education/edan75/part2.pdf
+- [[[github-avr_llvm-issues-88,83]]] https://github.com/avr-llvm/llvm/issues/88
+- [[[asciidoctor-quickref,84]]] https://asciidoctor.org/docs/asciidoc-syntax-quick-reference/
+- [[[llvm_phabricator-d56351,85]]] https://reviews.llvm.org/D56351
+- [[[hatenablog-rhysd-230119,86]]] https://rhysd.hatenablog.com/entry/2017/03/13/230119
+- [[[llvm_dev_ml-115805,87]]] http://lists.llvm.org/pipermail/llvm-dev/2017-July/115805.html
+- [[[github_riscv-llvm_patch_29,88]]] https://github.com/lowRISC/riscv-llvm/blob/master/0029-RISCV-Add-support-for-llvm.-frameaddress-returnaddre.patch
+- [[[github-riscv_llvm-clang,89]]] https://github.com/lowRISC/riscv-llvm/tree/master/clang
+- [[[github-elvm_clang,90]]] https://github.com/shinh/clang/tree/elvm
+- [[[github_riscv-llvm_patch_22,91]]] https://github.com/lowRISC/riscv-llvm/blob/master/0022-RISCV-Support-lowering-FrameIndex.patch
+- [[[llvm_dev_ml-087879,92]]] http://lists.llvm.org/pipermail/llvm-dev/2015-July/087879.html
+- [[[stackoverflow-27467293,93]]] https://stackoverflow.com/questions/27467293/how-to-force-clang-use-llvm-assembler-instead-of-system
+- [[[github-riscv_llvm-clang-03,94]]] https://github.com/lowRISC/riscv-llvm/blob/master/clang/0003-RISCV-Implement-clang-driver-for-the-baremetal-RISCV.patch
+- [[[github_riscv-llvm_patch_25,95]]] https://github.com/lowRISC/riscv-llvm/blob/master/0025-RISCV-Add-custom-CC_RISCV-calling-convention-and-imp.patch
+- [[[llvm_dev_ml-106187,96]]] http://lists.llvm.org/pipermail/llvm-dev/2016-October/106187.html
+- [[[llvm_phabricator-d39322,97]]] https://reviews.llvm.org/D39322
+- [[[cpu0-lld,98]]] http://jonathan2251.github.io/lbt/lld.html
+- [[[youtube-how_to_add_a_new_target_to_lld,99]]] https://www.youtube.com/watch?v=FIXaeRU31Ww
+- [[[llvm-smith_newlldtargetpdf,100]]] https://llvm.org/devmtg/2016-09/slides/Smith-NewLLDTarget.pdf
+- [[[llvm-lld,101]]] https://lld.llvm.org/index.html
+- [[[note-n9948f0cc3ed3,102]]] https://note.mu/ruiu/n/n9948f0cc3ed3
+- [[[lanai-isa,103]]] https://docs.google.com/document/d/1jwAc-Rbw1Mn7Dbn2oEB3-0FQNOwqNPslZa-NDy8wGRo/pub
+- [[[github-blog_os-issues-370,104]]] https://github.com/phil-opp/blog_os/issues/370
+- [[[llvm_phabricator-d61688,105]]] https://reviews.llvm.org/D61688
+- [[[man-xtensa_linux_gnu_ld,106]]] https://linux.die.net/man/1/xtensa-linux-gnu-ld
+- [[[man-elf,107]]] https://linuxjm.osdn.jp/html/LDP_man-pages/man5/elf.5.html
+- [[[llvm_phabricator-d45385,108]]] https://reviews.llvm.org/D45385
+- [[[llvm_phabricator-d47882,109]]] https://reviews.llvm.org/D47882
+- [[[llvm_dev_ml-128257,110]]] https://lists.llvm.org/pipermail/llvm-dev/2018-December/128257.html
+- [[[github_riscv-llvm_patch_31,111]]] https://github.com/lowRISC/riscv-llvm/blob/master/0031-RISCV-Implement-support-for-the-BranchRelaxation-pas.patch
+- [[[github_riscv-llvm_patch_30,112]]] https://github.com/lowRISC/riscv-llvm/blob/master/0030-RISCV-Implement-branch-analysis.patch
+- [[[stackoverflow-5789806,113]]] https://stackoverflow.com/questions/5789806/meaning-of-and-in-c
+- [[[compiler_study_report,114]]] https://proc-cpuinfo.fixstars.com/2018/11/compiler_study_report/
+- [[[github-llvm-bcb36be8e3f5dced36710ba1a2e2206071ccc7ba,115]]] https://github.com/llvm/llvm-project/commit/bcb36be8e3f5dced36710ba1a2e2206071ccc7ba
+- [[[llvm_dev_ml-059799,116]]] http://lists.llvm.org/pipermail/llvm-dev/2013-February/059799.html
+- [[[tricore-llvm-slides,117]]] https://reup.dmcs.pl/wiki/images/7/7a/Tricore-llvm-slides.pdf
+- [[[tricore-llvm,118]]] https://opus4.kobv.de/opus4-fau/files/1108/tricore_llvm.pdf
+- [[[llvm_dev_ml-111697,119]]] http://lists.llvm.org/pipermail/llvm-dev/2017-April/111697.html
+- [[[takayuki-no09,120]]] http://www.ertl.jp/~takayuki/readings/c/no09.html
+- [[[hwenginner-linker,121]]] https://hwengineer.github.io/linker/
+- [[[koikikukan-000300,122]]] http://www.koikikukan.com/archives/2017/04/05-000300.php
+- [[[stackoverflow-57735654_34997577,123]]] https://stackoverflow.com/questions/34997577/linker-script-allocation-of-bss-section#comment57735654_34997577
+- [[[redhat-ld_simple_example,124]]] https://access.redhat.com/documentation/en-US/Red_Hat_Enterprise_Linux/4/html/Using_ld_the_GNU_Linker/simple-example.html
+- [[[llvm_phabricator-d45395,125]]] https://reviews.llvm.org/D45395
+- [[[llvm_phabricator-d45395-398662,126]]] https://reviews.llvm.org/D45395#inline-398662
+- [[[llvm-langref-inline_asm,127]]] http://llvm.org/docs/LangRef.html#inline-assembler-expressions
+- [[[hazymoon-gcc_inline_asm,128]]] http://caspar.hazymoon.jp/OpenBSD/annex/gcc_inline_asm.html
+- [[[github_riscv-llvm_patch_28,129]]] https://github.com/lowRISC/riscv-llvm/blob/master/0028-RISCV-Add-basic-support-for-inline-asm-constraints.patch
+- [[[llvm-langref-inline_asm-asm_template_argument_modifier,130]]] http://llvm.org/docs/LangRef.html#asm-template-argument-modifiers
+- [[[github-llvm-0715d35ed5ac2312951976bee2a0d2587f98f39f,131]]] https://github.com/llvm/llvm-project/commit/0715d35ed5ac2312951976bee2a0d2587f98f39f
+- [[[github_riscv-llvm_patch_32,132]]] https://github.com/lowRISC/riscv-llvm/blob/master/0032-RISCV-Reserve-an-emergency-spill-slot-for-the-regist.patch
+- [[[github_riscv-llvm_patch_26,133]]] https://github.com/lowRISC/riscv-llvm/blob/master/0026-RISCV-Support-for-varargs.patch
+- [[[github-fracture-wiki-how-dagisel-works,134]]] https://github.com/draperlaboratory/fracture/wiki/How-TableGen%27s-DAGISel-Backend-Works
+- [[[welcome_to_the_back_end-slides,135]]] http://llvm.org/devmtg/2017-10/slides/Braun-Welcome%20to%20the%20Back%20End.pdf
+- [[[life_of_an_instruction,136]]] https://eli.thegreenplace.net/2012/11/24/life-of-an-instruction-in-llvm/
+- [[[shinh-blog-010637,137]]] http://shinh.hatenablog.com/entry/2014/10/03/010637
+- [[[llvm_backend_intro,138]]] https://www.slideshare.net/AkiraMaruoka/llvm-backend
+- [[[amazon-llvm_cookbook-customer_review,139]]] https://www.amazon.co.jp/dp/178528598X#customer_review-R28L2NAL8T9M2H
+- [[[llvm_dev_ml-117139,140]]] https://lists.llvm.org/pipermail/llvm-dev/2017-September/117139.html
+- [[[github_riscv-llvm_patch_85,141]]] https://github.com/lowRISC/riscv-llvm/blob/master/0085-RISCV-Set-AllowRegisterRenaming-1.patch
+- [[[llvm_dev_ml-135337,142]]] https://lists.llvm.org/pipermail/llvm-dev/2019-September/135337.html
+- [[[wikipedia-weak_symbol,143]]] https://en.wikipedia.org/wiki/Weak_symbol
+- [[[wikipedia-remat,144]]] https://en.wikipedia.org/wiki/Rematerialization
+- [[[llvm_phabricator-d46182,145]]] https://reviews.llvm.org/D46182
+- [[[nakata-compiler,146]]] 『コンパイラの構成と最適化（第2版）』（中田育男、朝倉書店、2009）
+- [[[fpga_develop_diary-to_llvm9,147]]] http://msyksphinz.hatenablog.com/entry/2019/08/17/040000
+- [[[llvm_phabricator-d60488,148]]] https://reviews.llvm.org/D60488
+- [[[llvm_phabricator-rl364191,149]]] https://reviews.llvm.org/rL364191
+- [[[llvm_phabricator-d64121,150]]] https://reviews.llvm.org/D64121
+- [[[llvm-codingstandards,151]]] https://llvm.org/docs/CodingStandards.html
+- [[[llvm_dev_ml-134921,152]]] https://lists.llvm.org/pipermail/llvm-dev/2019-September/134921.html
+- [[[llvm_phabricator-d43256,153]]] https://reviews.llvm.org/D43256
+- [[[llvm_dev_ml-114675,154]]] http://lists.llvm.org/pipermail/llvm-dev/2017-June/114675.html
+- [[[llvm_phabricator-d42780,155]]] https://reviews.llvm.org/D42780
+- [[[llvm_phabricator-d51732,156]]] https://reviews.llvm.org/D51732
+- [[[llvm_devmtg-schedmachinemodel,157]]] http://llvm.org/devmtg/2014-10/Slides/Estes-MISchedulerTutorial.pdf
+- [[[llvm_dev_ml-098535,158]]] https://lists.llvm.org/pipermail/llvm-dev/2016-April/098535.html
+- [[[llvm_devmtg-writinggreatsched,159]]] https://www.youtube.com/watch?v=brpomKUynEA
+- [[[anandtech-11441,160]]] https://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55/4
+- [[[llvm_devmtg-larintrick,161]]] https://llvm.org/devmtg/2012-11/Larin-Trick-Scheduling.pdf
+- [[[llvm-schedinorder,162]]] https://llvm.org/devmtg/2016-09/slides/Absar-SchedulingInOrder.pdf
+- [[[llvm_2003f,163]]] http://na2co3.exp.jp/llvm-2003f-fib-trace.html
+- [[[msyksphinz_github_io-llvm,164]]] https://msyksphinz.github.io/github_pages/llvm/
+- [[[llvm_phabricator-d86505,165]]] https://reviews.llvm.org/D86505
+- [[[llvm_phabricator-d86269,166]]] https://reviews.llvm.org/D86269
+- [[[github_csky,167]]] https://github.com/c-sky
+- [[[llvm_phabricator-d69103,168]]] https://reviews.llvm.org/D69103
+- [[[llvm_phabricator-rG9218ff50f93085d0a16a974db28ca8f14bc66f64,169]]] https://reviews.llvm.org/rG9218ff50f93085d0a16a974db28ca8f14bc66f64
+- [[[llvm_phabricator-d95315,170]]] https://reviews.llvm.org/D95315
+- [[[github_llvm_00ecf67045231743ef58950f3d3f4fbe450b8e0a,171]]] https://github.com/llvm/llvm-project/commit/00ecf67045231743ef58950f3d3f4fbe450b8e0a